A Negative-Overhead, Self-Timed Pipeline

نویسندگان

  • Mark R. Greenstreet
  • Brian D. Winters
چکیده

This paper presents a novel variation of wave pipelining that we call “surfing.” In previous wave pipelined designs, timing uncertainty grows monotonically as events propagate through gates or other logic elements. We bound this dispersion by propagating a timing pulse along with the data values. Our logic elements have delays that are smaller in the presence of the pulse than in its absence. This produces a “surfing” effect: events are bound in close proximity to the timing pulse. We demonstrate this approach with the design of a 4 12 multiplier. Spice simulations from the extracted layout indicate that this design is robust in the presence of fabrication parameter variation and power supply noise. Because timing is maintained by accelerating the logic, our designs achieve lower latency than their purely combinational equivalents. Thus, the control overhead for these designs is indeed negative. Appeared in Proceedings of Eighth International Symposium on Advanced Research in Asynchronous Circuits and Systems, April 2002.

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A Low Latency Asynchronous FIFO Combining a Wave Pipeline with a Handshake Scheme

This paper presents a new asynchronous FIFO design to reduce forward latency in a linear structure. The operation mode for each cell can be reconfigured dynamically as either of the two schemes, wave pipelining or handshaking, according to the data flow in the FIFO. The adoption of wave pipelining to the conventional self-timed FIFO can reduce the overhead of the handshaking as well as latching...

متن کامل

Self-Timed Power-Aware Pipeline Chip and Its Evaluation

This paper describes an experimental chip of self-timed (clockless) power-aware pipeline incorporating stage-by-stage power gating scheme. Its power gating circuit cuts the voltage-supply to the idle pipeline stages in order to reduce the static (leakage) power dissipation. To reduce the dynamic power dissipation, self-timed pipeline (STP) is one of the suitable circuit architectures because it...

متن کامل

Low-Powered Self-Timed Pipeline with Runtime Fine-Grain Power Supply

This paper describes a runtime fine-grain power supply scheme based on the self-timed pipeline (STP) circuits. The STP works with its local hand-shake signal so that it does not require the global clock distribution, i.e., centralized control. Therefore, various power supply control for the STP can be naturally localized in both spatial and temporal domains without stopping its effective data t...

متن کامل

SP 25.7: Skew-Tolerant Domino Circuits

As cycle time of chips shrinks and die size grows, clock skew measured as a fraction of the cycle time is increasing. Traditional domino circuits shown in Figure 1 are especially sensitive because skew must be budgeted in both half-cycles. The problem with such domino pipelines is that evaluation starts (indicated by the heavy dashed line) when the clock connected to the first gate in the half-...

متن کامل

Efficient Implementation of Parallel Self-Timed Adder Using Verilog HDL

Many pipelined adaptive signal processing systems are subject to a trade-off between throughput and signal processing performance incurred by the pipelined adaptation feedback loops. In the conventional synchronous design regime, such throughput/performance trade-off is typically fixed since the pipeline depth is usually determined in the design phase and remains unchanged in the run time. Neve...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2002